View UPD62A_5520.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD62A
4-BIT SINGLE-CHIP MICROCONTROLLER FOR INFRARED REMOTE CONTROL TRANSMISSION
DESCRIPTION
Due to its low-voltage 2.0 V operation, on-chip carrier generator for infrared remote control transmission, standby release function through key entry, and programmable timer, the PD62A is ideal for infrared remote control transmitters. For the PD62A, the one-time PROM product PD6P4B has been made available for program evaluation or small-scale production.
FEATURES
* Program memory (ROM): 512 x 10 bits * Data memory (RAM): 32 x 4 bits * On-chip carrier generator for infrared remote control * 9-bit programmable timer: * Command execution time: * Stack levels: * I/O pins (KI/O): * Input pins (KI): * Sense input pin (S0) * S1/LED pin (I/O): When in output mode, this is the remote control transmission display pin. * Power supply voltage: * Oscillator frequency: VDD = 2.0 to 3.6 V fX = 2.4 to 8 MHz * Operating ambient temperature: TA = -40 to +85C * POC (Power On Clear) circuit (Mask option) 1 channel 8 s (when operating at fX = 8 MHz: ceramic oscillation) 1 (Stack RAM is also available for data memory RF.) 8 4
APPLICATION
Infrared remote control transmitter (for AV and household electrical appliances)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14474EJ1V0DS00 (1st edition) Date Published November 1999 N CP(K) Printed in Japan
(c)
1999
PD62A
ORDERING INFORMATION
Part Number Package 20-pin plastic SSOP (300 mils)
PD62AMC-xxx-5A4
Remark xxx indicates ROM code suffix.
PIN CONFIGURATION (TOP VIEW)
20-pin Plastic SSOP (300 mils) * PD62AMC-xxx-5A4
KI/O6 KI/O7 S0 S1/LED REM VDD XOUT XIN GND RESET
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0
Caution The order of the KI and KI/O pin numbers is the reverse of that of the PD6600A and 6124A.
2
Data Sheet U14474EJ1V0DS00
PD62A
BLOCK DIAGRAM
REM Carrier generator 4 CPU core ROM 8 S1/LED 9-bit timer Port KI/O 8 KI/O0-KI/O7 Port KI 4 KI0-KI3
2
Port S
2
S0, S1/LED
RAM
RESET System control XIN XOUT VDD GND
LIST OF FUNCTIONS
Item ROM capacity 512 x 10 bits Mask ROM RAM capacity Stack I/O pins 32 x 4 bits 1 level (RAM also used as RF) * * * * Key input (KI): Key I/O (KI/O): Key extended input (S0, S1): Remote control transmission display output (LED): 4 8 2 1 (alternately functions as S1 pin)
PD62A
1002 x 10 bits
PD6P4B
One-time PROM
Number of keys
* 32 keys * 48 keys (when extended by key extension input) * 96 keys (when extended by key extension input and diode) Ceramic oscillation * fX = 2.4 to 8 MHz 8 s (fX = 8 MHz) fX/8, fX/16, fX/64, fX/96, fX/128, fX/192, no carrier (high level) 9-bit programmable timer: 1 channel Mask option VDD = 2.0 to 3.6 V TA = -40 to +85C * 20-pin plastic SSOP (300 mils) * 20-pin plastic SOP (300 mils) * 20-pin plastic SSOP (300 mils) Internal VDD = 2.2 to 3.6 V (fX = 2.4 to 4 MHz) VDD = 2.7 to 3.6 V (fX = 4 to 8 MHz)
Clock frequency Instruction execution time Carrier frequency Timer POC circuit Supply voltage Operating ambient temperature Package
Data Sheet U14474EJ1V0DS00
3
PD62A
TABLE OF CONTENTS 1. PIN FUNCTIONS ..........................................................................................................................
1.1 1.2 1.3 List of Pin Functions ......................................................................................................................... Pin Input/Output Circuits .................................................................................................................. Recommended Connection of Unused Pins ...................................................................................
6
6 7 8
2. INTERNAL CPU FUNCTIONS .....................................................................................................
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Program Counter (PC) ...................................................................................................................... Stack Pointer (SP) ............................................................................................................................. Address Stack Register (ASR (RF)) .................................................................................................
9
9 9 9
Program Memory (ROM) ................................................................................................................... 10 Data Memory (RAM) .......................................................................................................................... 10 Data Pointer (DP) ............................................................................................................................... 11 Accumulator (A) ................................................................................................................................ 11 Arithmetic and Logic Unit (ALU) ...................................................................................................... 12 Flags ................................................................................................................................................... 12 2.9.1 2.9.2 Status flag (F) .......................................................................................................................... 12 Carry flag (CY) ........................................................................................................................ 13
3. PORT REGISTERS (PX) .............................................................................................................. 14
3.1 3.2 KI/O Port (P0) ....................................................................................................................................... 15 KI Port/Special Ports (P1) ................................................................................................................. 16 3.2.1 3.2.2 3.2.3 3.3 3.4 KI port (P11: bits 4 to 7 of P1) .................................................................................................. 16 S0 port (bit 2 of P1) .................................................................................................................. 16 S1/LED (bit 3 of P1) ................................................................................................................. 16
Control Register 0 (P3) ..................................................................................................................... 17 Control Register 1 (P4) ..................................................................................................................... 18
4. TIMER ........................................................................................................................................... 19
4.1 4.2 4.3 4.4 Timer Configuration .......................................................................................................................... 19 Timer Operation ................................................................................................................................. 20 Carrier Output .................................................................................................................................... 21 Software Control of Timer Output ................................................................................................... 21
5. STANDBY FUNCTION ................................................................................................................. 22
5.1 5.2 5.3 Outline of Standby Function ............................................................................................................ 22 Standby Mode Setting and Release ................................................................................................. 23 Standby Mode Release Timing ........................................................................................................ 24
6. RESET PIN ................................................................................................................................... 26 7. POC CIRCUIT (MASK OPTION) .................................................................................................. 27
7.1 7.2 Functions of POC Circuit .................................................................................................................. 28 Oscillation Check at Low Supply Voltage ....................................................................................... 28
8. SYSTEM CLOCK OSCILLATOR ................................................................................................. 29
4
Data Sheet U14474EJ1V0DS00
PD62A
9. INSTRUCTION SET ...................................................................................................................... 30
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Machine Language Output by Assembler ....................................................................................... 30 Circuit Symbol Description .............................................................................................................. 31 Mnemonic to/from Machine Language (Assembler Output) Contrast Table ............................... 32 Accumulator Operation Instructions ............................................................................................... 36 Input/Output Instructions ................................................................................................................. 39 Data Transfer Instruction .................................................................................................................. 40 Branch Instructions .......................................................................................................................... 42 Subroutine Instructions .................................................................................................................... 43 Timer Operation Instructions ........................................................................................................... 44
9.10 Others ................................................................................................................................................. 45
10. ASSEMBLER RESERVED WORDS .......................................................................................... 47
10.1 Mask Option Directives .................................................................................................................... 47 10.1.1 OPTION and ENDOP directives ............................................................................................. 47 10.1.2 Mask option definition directive ............................................................................................... 47
11. ELECTRICAL SPECIFICATIONS .............................................................................................. 48 12. CHARACTERISTIC CURVES (REFERENCE VALUES) ........................................................... 52 13. APPLICATION CIRCUIT EXAMPLE .......................................................................................... 53 14. PACKAGE DRAWINGS ............................................................................................................. 54 15. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 55 APPENDIX A. DEVELOPMENT TOOLS ......................................................................................... 56 APPENDIX B. FUNCTIONAL COMPARISON BETWEEN PD62A AND OTHER SUBSERIES ... 57 APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT .......................... 58
Data Sheet U14474EJ1V0DS00
5
PD62A
1. PIN FUNCTIONS 1.1 List of Pin Functions
Pin No. 1 2 15 to 20 Symbol Function After Format CMOS push-pullNote 1 After Reset High-level output
KI/O0 to KI/O7 8-bit input/output port Input/output can be specified in 8-bit units. In input mode, a pull-down resistor is added. In output mode, these pins can be used as the key scan output of the key matrix. S0 Input port Can also be used as the key return input of the key matrix. In input mode, the use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. If input mode is canceled by software, this pin is placed in OFF mode and enters the high-impedance state. Input/output port In input mode (S1), this pin can also be used as the key return input of the key matrix. The use of a pull-down resistor for the S0 and S1 ports can be specified by software in 2-bit units. In output mode (LED), it becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs a low level from the LED output synchronously with the REM signal. Infrared remote control transmission output. The output is active high. Carrier frequency: fX/8, fX/64, fX/96, high-level, fX/16, fX/128, fX/192 (software supporting) Power supply These pins are connected to system clock ceramic resonators. Ground Normally, this pin is the system reset input. By inputting a low level, the CPU can be reset. When resetting with the POC circuit (mask option) a low level is output. A pull-up resistor is connected to this pin.
3
--
High-impedance (OFF mode)
4
S1/LED
CMOS push-pull
High-level output (LED)
5
REM
CMOS push-pull
Low-level output
6 7 8 9 10
VDD XOUT XIN GND RESET
-- -- -- --
-- Low level (oscillation stopped) -- --
11 to 14
KI0 to KI3Note 2 4-bit input port These pins can be used as the key return input of the key matrix. The use of a pull-down resistor can be specified by software in 4-bit units.
--
Input (low-level)
Notes 1. Be aware that the drive capability of the low-level output side is held low. 2. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is released (when the RESET pin changes from low level to high level, or POC is released due to supply voltage startup).
6
Data Sheet U14474EJ1V0DS00
PD62A
1.2 Pin Input/Output Circuits
The input/output circuits of the PD62A pins are shown in partially simplified forms below. (1) KI/O0 to KI/O7
VDD Data Output latch
(4) S0
Input buffer
P-ch
OFF mode
Output disable
Selector
N-chNote
Standby release Pull-down flag N-ch
Input buffer
N-ch
(5) S1/LED Note The drive capability is held low. (2) KI0 to KI3
Standby release Input buffer
VDD REM output latch
P-ch
Output disable Standby release Input buffer
N-ch
Pull-down flag
N-ch
Pull-down flag
N-ch
(3) REM
(6) RESET
VDD
VDD
P-ch
P-ch Data Output latch N-ch
Carrier generator
Input buffer Internal reset signal other than POC N-ch
POC circuit
Mask option
Data Sheet U14474EJ1V0DS00
7
PD62A
1.3 Recommended Connection of Unused Pins
The following connections are recommended for unused pins. Table 1-1. Connections for Unused Pins
Connection Inside the Microcontroller KI/O Input mode Output mode REM S1/LED S0 KI RESETNote -- High-level output -- Output mode (LED) setting OFF mode setting -- On-chip POC circuit Directly connect these pins to GND Leave open Outside the Microcontroller Leave open
Pin
Note For application circuits requiring high reliability, be sure to design so that the RESET signal is input externally. Caution It is recommended that the I/O mode and the terminal output level are fixed by repeating the settings in each loop of the program.
8
Data Sheet U14474EJ1V0DS00
PD62A
2. INTERNAL CPU FUNCTIONS 2.1 Program Counter (PC): 10 Bits
This is a binary counter that holds the address information of the program memory. Figure 2-1. Program Counter Configuration
PC PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
The program counter contains the address of the instruction that should be executed next. Normally, the counter contents are automatically incremented in accordance with the instruction length (byte count) each time an instruction is executed. However, when executing JUMP instructions (JMP, JC, JNC, JF, JNF), the program counter contains the jump destination address written in the operand. When executing the subroutine call instruction (CALL), the call destination address written in the operand is entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to the PC. When reset, the value of the program counter becomes "000H".
2.2 Stack Pointer (SP): 1 Bit
This is a 1-bit register which holds the status of the address stack register. The stack pointer contents are incremented when the call instruction (CALL) is executed; they are decremented when the return instruction (RET) is executed. When reset, the stack pointer contents are cleared to 0. When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is hung up and a system reset signal is generated, and the PC becomes "000H". As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer by means of a program.
2.3 Address Stack Register (ASR (RF)): 10 Bits
The address stack register saves the return address of the program after a subroutine call instruction is executed. The low-order 8 bits are configured as RAM that is also used as the data memory RF. The register holds the ASR value even after RET is executed. When reset, it holds the previous data (undefined on power application). Caution If RF is accessed as data memory, the high-order 2 bits of the ASR become undefined. Figure 2-2. Address Stack Register Configuration
RF ASR ASR9 ASR8 ASR7 ASR6 ASR5 ASR4 ASR3 ASR2 ASR1 ASR0
Data Sheet U14474EJ1V0DS00
9
PD62A
2.4 Program Memory (ROM): 512 steps x 10 bits
The ROM consists of 10 bits per step, and is addressed by the program counter. The program memory stores programs and table data, etc. The 22 steps from 3EAH to 3FFH cannot be used in the test program area. Figure 2-3. Program Memory Map
10 bits 000H
0FFH 100H
1FFH 200H
Unmounted areaNote
3E9H 3EAH 3FFH
Test program areaNote
Note The unmounted area and the test program area are so designed that a program or data placed in either of them by mistake is returned to the 000H address.
2.5 Data Memory (RAM): 32 x 4 Bits
The data memory, which is a static RAM consisting of 32 x 4 bits, is used to retain processed data. The data memory is sometimes processed in 8-bit units. R0 can be used as the ROM data pointer. RF is also used as the ASR. When reset, R0 is cleared to "00H" and R1 to RF retain the previous data (undefined upon power application).
10
Data Sheet U14474EJ1V0DS00
PD62A
Figure 2-4. Data Memory Configuration
R1n (high-order 4 bits) R0n (low-order 4 bits) DP (refer to 2.6 Data Pointer (DP)) R0 R10 R00 R1 R11 R01 R2 R12 R02 R3 R13 R03 R4 R14 R04 R5 R15 R05 R6 R16 R06 R7 R17 R07 R8 R18 R08 R9 R19 R09 RA R1A R0A RB R1B R0B RC R1C R0C RD R1D R0D RE R1E R0E RF R1F R0F ASR (refer to 2.3 Address Stack Register (ASR (RF)))
2.6 Data Pointer (DP): 10 Bits
The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents. The low-order 8 bits of the ROM address are specified by R0 of the data memory; and the high-order 2 bits by bits 4 and 5 of the P3 register (CR0). When reset, the pointer contents become "000H". Figure 2-5. Data Pointer Configuration
P3 register b5 P3 DP9 b4 DP8 DP7 DP6 R10 DP5 DP4 DP3 DP2 R00 DP1 DP0 R0
2.7 Accumulator (A): 4 Bits
The accumulator, which is a register consisting of 4 bits, plays a leading role in performing various operations. When reset, the accumulator contents become undefined. Figure 2-6. Accumulator Configuration
A3
A2
A1
A0
A
Data Sheet U14474EJ1V0DS00
11
PD62A
2.8 Arithmetic and Logic Unit (ALU): 4 Bits
The arithmetic and logic unit (ALU), which is an arithmetic circuit consisting of 4 bits, executes simple manipulations with priority given to logical operations.
2.9 Flags
2.9.1 Status flag (F) Pin and timer statuses can be checked by executing the STTS instruction to check the status flag. The status flag is set (to 1) in the following cases. * If the condition specified with the operand is met when the STTS instruction has been executed * When standby mode is canceled. * When the cancelation condition is met at the point of executing the HALT instruction. (In this case, the system is not placed in standby mode.) Conversely, the status flag is cleared (to 0) in the following cases: * If the condition specified with the operand is not met when the STTS instruction has been executed. * When the status flag has been set (to 1), the HALT instruction executed, but the cancelation condition is not met at the point of executing the HALT instruction. (In this case, the system is not placed in standby mode.) Table 2-1. Conditions for Status Flag (F) to Be Set by STTS Instruction
Operand Value of STTS Instruction b3 0 b2 0 0 1 1 1 b1 0 1 1 0 b0 0 1 0 1 High level input to at least one of KI pins. High level input to at least one of KI pins. High level input to at least one of KI pins. The down counter of the timer is 0. [The following condition is added in addition to the above.] High level input to at least one of S0 and S1 pins.
Condition for Status Flag (F) to Be Set
Any combination of b2, b1, and b0 above.
12
Data Sheet U14474EJ1V0DS00
PD62A
2.9.2 Carry flag (CY) The carry flag is set (to 1) in the following cases: * If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is "1" and bit 3 of the operand is "1". * If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is "1". * If the INC instruction or the SCAF instruction is executed when the value of the accumulator is 0FH. The carry flag is cleared (to 0) in the following cases: * If the ANL instruction or the XRL instruction is executed when at least either bit 3 of the accumulator or bit 3 of the operand is "0". * If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is "0". * If the INC instruction or the SCAF instruction is executed when the value of the accumulator is other than 0FH. * If the ORL instruction is executed. * When data is written to the accumulator by the MOV instruction or the IN instruction.
Data Sheet U14474EJ1V0DS00
13
PD62A
3. PORT REGISTERS (PX)
The KI/O port, the KI port, the special ports (S0, S1/LED), and the control registers are treated as port registers. The port register values after reset are shown below. Figure 3-1. Port Register Configuration
Port Register P0 P10 KI/O7 KI/O6 KI/O5 KI/O4 P1 P11 KI3 KI2 KI1 KI0 S1/LED S0 P01 1 1 03H P03 DP9 DP8 TCTL CARY MOD1 MOD0 26H P04 0
S1/LED mode KI/O mode
After Reset FFH P00
KI/O3
KI/O2
KI/O1
KI/O0 x FHNote
P3 (Control register 0) P13 0 0
P4 (Control register 1) P14 0 0 KI S0/S1 pull-down pull-down
S0 mode
Note
x: Refers to the value based on the KI pin status. Table 3-1. Relationship Between Ports and Read/Write
Input Mode Read KI/O KI S0 S1/LED Pin status Pin status Pin status Pin status Write Output latch -- -- -- Note Pin status Output Mode Read Output latch -- Write Output latch -- -- --
Port Name
Note When in OFF mode, "1" is normally read.
14
Data Sheet U14474EJ1V0DS00
PD62A
3.1 KI/O Port (P0)
The KI/O port is an 8-bit input/output port for key scan output. Input/output mode is set by bit 1 of the P4 register. If a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can be read in output mode. If the write instruction is executed, data can be written to the output latch regardless of input or output mode. When reset, the port is placed in output mode; and the value of the output latch (P0) becomes 1111 1111B. The KI/O port includes a pull-down resistor, allowing pull-down in input mode only. Caution If a key is double-pressed, a high-level output and a low-level output may coincide at the KI/O port. To avoid this, the low-level output current of the KI/O port is held low. Therefore, be careful when using the KI/O port for purposes other than key scan output. The KI/O port is so designed that, even when connected directly to VDD, within the normal supply voltage range (VDD = 2.0 to 3.6 V), no problem may occur. Table 3-2. KI/O Port (P0)
Bit Name b7 KI/O7 b6 KI/O6 b5 KI/O5 b4 KI/O4 b3 KI/O3 b2 KI/O2 b1 KI/O1 b0 KI/O0
b0 to b7: Read: Write:
In input mode, the KI/O pin's state is read. In output mode, the KI/O pin's output latch contents are read. Data is written to the KI/O pin's output latch regardless of input or output mode.
Data Sheet U14474EJ1V0DS00
15
PD62A
3.2 KI Port/Special Ports (P1)
3.2.1 KI port (P11: bits 4 to 7 of P1) The KI port is a 4-bit input port for key entry. The pin status can be read at this port. Software can be used to set whether to connect a pull-down resistor at the KI port in 4-bit units by means of bit 5 of the P4 register. When reset, a pull-down resistor is connected. Table 3-3. KI/Special Port Register (P1)
Bit Name b7 KI3 b6 KI2 b5 KI1 b4 KI0 b3 S1/LED b2 S0 b1 b0
(Fixed to 1)
b2: b3: b4 to b7:
In input mode, the status of the S0 pin is read (Read only). In OFF mode, this bit is fixed to 1. The status of the S1/LED pin is read regardless of input/output mode (Read only). The status of the KI pin is read (Read only).
Caution In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is released (when the RESET pin changes from low level to high level, or POC is released due to supply voltage startup). 3.2.2 S0 port (bit 2 of P1) The S0 port is the input/OFF mode port. The pin status can be read by setting this port to input mode with bit 0 of the P4 register. In input mode, software can be used to set whether to connect a pull-down resistor at the S0 and S1/LED ports in 2-bit units by means of bit 4 of the P4 register. If input mode is canceled (set to OFF mode), the pin becomes high-impedance, but the through current is stopped from flowing internally. In OFF mode, "1" can be read regardless of the pin status. When reset, this port is set to OFF mode and becomes high-impedance. 3.2.3 S1/LED (bit 3 of P1) The S1/LED port is an input/output port. This port is set input or output mode by means of bit 2 of the P4 register. The pin status can be read in both input and output mode. In input mode, software can be used to set whether to connect a pull-down resistor at the S0 and S1/LED ports in 2-bit units by means of bit 4 of the P4 register. In output mode, the pull-down resistor is automatically disconnected, and this port becomes the remote control transmission display pin (refer to 4. TIMER). When reset, this port is placed in output mode, and a high level is output.
16
Data Sheet U14474EJ1V0DS00
PD62A
3.3 Control Register 0 (P3)
Control register 0 consists of 8 bits. The contents that can be controlled are as shown below. When reset, this register becomes 0000 0011B. Table 3-4. Control Register 0 (P3)
Bit Name b7 -- b6 -- b5 b4 b3 b2 CARY b1 MOD1 b0 MOD0
DP (Data pointer) TCTL DP9 DP8 0 1 0 1/1 1/2 0
Set value After reset
0 1
Fixed to 0 0
Fixed to 0 0
0 1 0
ON OFF 0
Refer to Table 3-5.
1
1
b0 and b1: These bits specify the carrier frequency and duty ratio of the REM output. b2: b3: This bit specifies the availability of the carrier of the frequency specified by b0 and b1. "0" = ON (with carrier); "1" = OFF (without carrier; high level) This bit changes the carrier frequency and the timer clock's frequency division ratio. "0" = 1/1 (carrier frequency: the specified value of b0 and b1; timer clock: fX/64) "1" = 1/2 (carrier frequency: half of the specified value of b0 and b1; timer clock: fX/128) Table 3-5. Timer Clock and Carrier Frequency Settings
b3 0 0 b2 0 0 1 1 1 0 0 x 0 0 1 1 1 x b1 0 1 0 1 x 0 1 0 1 x fX/128 b0 Timer Clock fX/64 Carrier Frequency (Duty Ratio) fX/8 (Duty 1/2) fX/64 (Duty 1/2) fX/96 (Duty 1/2) fX/96 (Duty 1/3) Without carrier (high level) fX/16 (Duty 1/2) fX/128 (Duty 1/2) fX/192 (Duty 1/2) fX/192 (Duty 1/3) Without carrier (high level)
b4 and b5: These bits specify the high-order 2 bits (DP8 and DP9) of the ROM data pointer. Remark x: don't care
Data Sheet U14474EJ1V0DS00
17
PD62A
3.4 Control Register 1 (P4)
Control register 1 consists of 8 bits. The contents that can be controlled are as shown below. When reset, this register becomes 0010 0110B. Table 3-6. Control Register 1 (P4)
Bit Name b7 -- b6 -- b5 KI b4 S0/S1 b3 -- b2 S1/LED mode Fixed to "0" 0 S1 LED 1 b1 KI/O mode IN OUT 1 b0 S0 mode OFF IN 0
Pull-down Pull-down Set value After reset 0 1 Fixed to 0 0 Fixed to 0 0 OFF ON 1 OFF ON 0
b0: Specifies the input mode of the S0 port. "0" = OFF mode (high impedance); "1" = IN (input mode). b1: Specifies the I/O mode of the KI/O port. "0" = IN (input mode); "1" = OUT (output mode). b2: Specifies the I/O mode of the S1/LED port. "0" = S1 (input mode); "1" = LED (output mode). b4: Specifies the connection of a pull-down resistor in S0/S1 port input mode. "0" = OFF (not connected); "1" = ON (connected) b5: Specifies the connections of a pull-down resistor in KI port. "0" = OFF (not connected); "1" = ON (connected). Remark In output mode or in OFF mode, all the pull-down resistors are automatically disconnected.
18
Data Sheet U14474EJ1V0DS00
PD62A
4. TIMER 4.1 Timer Configuration
The timer is the block used for creating a remote control transmission pattern. As shown in Figure 4-1, it consists of a 9-bit down counter (t8 to t0), a flag (t9) enabling 1-bit timer output, and a zero-detection circuit. Figure 4-1. Timer Configuration
T T1 t9 t8 t7 t6 T0 t5 t4 t3 t2 9-bit down counter t1 t0
Bit 3 of control register 0 (P3)
Selector
Count clock
fX/64 fX/128
S1/LED
Carrier synchronous circuit
Timer operation end signal (HALT # x101B release signal) Zero-detection circuit
REM
Bit 2 of control register 0 (P3) Carrier signal
Data Sheet U14474EJ1V0DS00
19
PD62A
4.2 Timer Operation
The timer starts (counting down) when a value other than 0 is set for the down counter with a timer operation instruction. The timer operation instructions for making the timer start operation are shown below: MOV T0, A MOV T1, A MOV T, #data10 MOV T, @R0 The down counter is decremented (-1) in the cycle of 64/fX or 128/fXNote. If the value of the down counter becomes 0, the zero-detection circuit generates the timer operation end signal to stop the timer operation. At this time, if the timer is in HALT mode (HALT #x101B) waiting for the timer to stop its operation, the HALT mode is canceled and the instruction following the HALT instruction is executed. The output of the timer operation end signal is continued while the down counter is 0 and the timer is stopped. There is the following relational expression between the timer's time and the down counter's set value. Timer time = (Set value + 1) x 64/fX (or 128/fXNote) Note This becomes 128/fX if bit 3 of the control register is set (to 1). By setting 1 for the flag (t9) which enables the timer output, the timer can output its operation status from the S1/LED pin and the REM pin. The REM pin can also output the carrier while the timer is in operation. Table 4-1. Timer Output (at t9 = 1)
S1/LED Pin Timer operating Timer halting L H REM Pin H (or carrier output Note) L
Note The carrier output results if bit 2 of control register 0 is cleared (to 0). Figure 4-2. Timer Output (When Carrier Is Not Output)
Timer value: (set value + 1) x 64/fX (or 128/fX)
LED
REM
20
Data Sheet U14474EJ1V0DS00
PD62A
4.3 Carrier Output
The carrier for remote-controlled transmission can be output from the REM pin by clearing (to 0) bit 2 of control register 0. As shown in Figure 4-3, in the case where the timer stops when the carrier is at a high level, the carrier continues to be output until its next fall and then stops due to the function of the carrier synchronous circuit. When the timer starts operation, however, the high-level width of the first carrier may be shorter than the specified width. Figure 4-3. Timer Output (When Carrier Is Output)
Timer value: (Set value+1) x 64/fX (or 128/fX)
LED
REM (at low-level start) Note 1 REM (at high-level start)
Note 2
Notes 1. Error when the REM output ends: Lead by "the carrier's low-level width" to lag by "the carrier's highlevel width" 2. Error of the carrier's high-level width: 0 to "the carrier's high-level width"
4.4 Software Control of Timer Output
The timer output can be controlled by software. As shown in Figure 4-4, a pulse with a minimum width of 1instruction cycle (64/fX) can be output. Figure 4-4. Pulse Output of 1-Instruction Cycle Width MOV T, #0000000000B; low-level output from the REM pin MOV T, #1000000000B; high-level output from the REM pin MOV T, #0000000000B; low-level output from the REM pin ... ... ...
64/fX
LED
REM
Data Sheet U14474EJ1V0DS00
21
PD62A
5. STANDBY FUNCTION 5.1 Outline of Standby Function
To save current consumption, two types of standby modes, HALT mode and STOP mode, are made available. In STOP mode, the system clock stops oscillation. At this time, the XIN and XOUT pins are fixed at a low level. In HALT mode, CPU operation halts, while the system clock continues oscillating. When in HALT mode, the timer (including REM output and LED output) operates. In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port register, etc. immediately before the standby mode was set are retained. Therefore, make sure to set the port status for the system so that the current consumption of the whole system is suppressed before the standby mode is set. Table 5-1. Statuses During Standby Mode
STOP Mode Setting instruction Clock oscillation circuit CPU Data memory Operation statuses Accumulator Flag F CY Port register Timer HALT instruction Oscillation stopped * Operation halted * Immediately preceding status retained * Immediately preceding status retained * 0 (When 1, the flag is not placed in the standby mode.) * Immediately preceding status retained * Immediately preceding status retained * Operation halted * Operable (The count value is reset to "0") Oscillation continues HALT Mode
Cautions 1. Write the NOP instruction as the first instruction after STOP mode is canceled. 2. When standby mode is canceled, the status flag (F) is set (to 1). 3. If, at the point the standby mode has been set, its cancelation condition is met, then the system is not placed in the standby mode. However, the status flag (F) is set (1).
22
Data Sheet U14474EJ1V0DS00
PD62A
5.2 Standby Mode Setting and Release
The standby mode is set with the HALT #b3b2b1b0B instruction for both STOP mode and HALT mode. For the standby mode to be set, the status flag (F) is required to have been cleared (to 0). The standby mode is released by the release condition specified by the reset (RESET input; POC) or the HALT instruction operand. If the standby mode is released, the status flag (F) is set (to 1). Even when the HALT instruction is executed in a state in which the status flag (F) has been set (to 1), the standby mode is not set. If the release condition is not met at this time, the status flag is cleared (to 0). If the release condition is met, the status flag remains set (to 1). Even in the case when the release condition has already been met at the point that the HALT instruction is executed, the standby mode is not set. Here, also, the status flag (F) is set (to 1). Caution Depending on the status of the status flag (F), the HALT instruction may not be executed. Be careful about this. For example, when setting HALT mode after checking the key status with the STTS instruction, because the system does not enter HALT mode as long as the status flag (F) remains set (to 1), sometimes an unintended operation is performed. In this case, the intended operation can be realized by executing the STTS instruction immediately after the timer setting to clear (to 0) the status flag. Example STTS MOV STTS HALT ... ... #03H T, #0xxH #05H #05H ;To check the KI pin status. ;To set the timer ;To clear the status flag ;To set HALT mode
(During this time, be sure not to execute an instruction that may set the status flag.)
Table 5-2. Addresses Executed After Standby Mode Release
Release Condition Reset Release condition shown in Table 5-3 Address Executed After Release 0 address The address following the HALT instruction
Data Sheet U14474EJ1V0DS00
23
PD62A
Table 5-3. Standby Mode Settings (HALT #b3b2b1b0B) and Release Conditions
Operand Value of HALT Instruction b3 0 b2 0 0 1 1 b1 0 1 1 b0 0 1 0 STOP STOP STOPNote 1 STOP All KI/O pins are high-level output. All KI/O pins are high-level output. The KI/O0 pin is high-level output. High level input to at least one of KI pins. High level input to at least one of KI pins. High level input to at least one of KI pins.
Setting Mode
Setting Precondition
Release Condition
Any combination of b2b1b0 above
[The following condition is added in addition to the above.] -- High level input to at least one of S0 and S1 pins Note 2.
0/1
1
0
1
HALT
--
When the timer's down counter is 0
Notes 1. When setting HALT #x110B, configure a key matrix by using the KI/O0 pin and the KI pin so that an internal reset takes effect at the time of program hang-up. 2. At least one of the S0 and S1 pins (the pin used for releasing standby) must be in input mode. (Note that an internal reset does not take effect even when both pins are in output mode.) Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value other than that above or when the precondition has not been satisfied when executing the HALT instruction. 2. If STOP mode is set when the timer's down counter is not 0 (timer operating), the system is placed in STOP mode only after all the 10 bits of the timer's down counter and the timer output permit flag are cleared to 0. 3. Write the NOP instruction as the first instruction after STOP mode is released.
5.3 Standby Mode Release Timing
(1) STOP mode release timing Figure 5-1. STOP Mode Cancelation by Release Condition
Wait (52/fX + )
HALT instruction (STOP mode) Standby release signal Operating mode STOP mode Oscillation stopped
HALT mode
Operating mode
Oscillation Clock
Oscillation : Oscillation growth time
Caution When a release condition is established in the STOP mode, the device is released from the STOP mode, and goes into a wait state. At this time, if the release condition is not held, the device goes into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP mode, it is necessary to hold the release condition longer than the wait time.
24
Data Sheet U14474EJ1V0DS00
PD62A
Figure 5-2. STOP Mode Release by RESET Input
HALT instruction (STOP mode) RESET Operating mode STOP mode Reset
Wait (246 to 694)/fX +
0 address start
HALT mode
Operating mode
Oscillation Clock
Oscillation stopped
Oscillation : Oscillation growth time
(2) HALT mode release timing Figure 5-3. HALT Mode Release by Cancelation Condition
Standby release signal
HALT instruction (HALT mode) Operating mode
HALT mode
Operating mode
Oscillation Clock
Figure 5-4. HALT Mode Release by RESET Input
HALT instruction (HALT mode) RESET Operating mode HALT mode Reset Oscillation stopped
Wait (246 to 694)/fX +
0 address start
HALT mode
Operating mode
Oscillation Clock
Oscillation : Oscillation growth time
Data Sheet U14474EJ1V0DS00
25
PD62A
6. RESET PIN
The system reset takes effect by inputting a low level to the RESET pin. While the RESET pin is at low level, the system clock oscillator is stopped and the XIN and XOUT pins are fixed to GND. If the RESET pin is raised from low level to high level, it executes the program from the 0 address after counting 246 to 694 of the system clock (fX). Figure 6-1. Reset Operation by RESET Input
Wait (246 to 694)/fX + RESET Operating mode or standby mode Oscillation stopped HALT mode
0 address start
Operating mode
: Oscillation growth time
The RESET pin outputs a low level when the POC circuit (mask option) is in operation. Caution When connecting a reset IC to the RESET pin, be sure to connect an IC of the N-ch open drain output type. Table 6-1. Hardware Statuses After Reset
* RESET Input During Operation * RESET Input in Standby Mode * Reset by Internal POC Circuit During Operation * Reset by Internal POC Circuit in Standby * Reset by Other Factors Note 1 Mode 000H 0B R0 = DP R1-RF 000H Undefined Undefined 0B 0B 000H P0 P1 Control register P3 P4 FFH xFHNote 2 03H 26H Previous status retained
Hardware PC (10 bits) SP (1 bit) Data memory
Accumulator (A) Status flag (F) Carry flag (CY) Timer (10 bits) Port register
Notes 1. The following resets are available. * Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy the precondition) * Reset when executing the RLZ instruction (when A = 0) * Reset by stack pointer's overflow or underflow 2. Refers to the value based on the KI pin status. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is released (when the RESET pin changes from low level to high level, or POC is released due to supply voltage startup).
26
Data Sheet U14474EJ1V0DS00
PD62A
7. POC CIRCUIT (MASK OPTION)
The POC circuit monitors the power supply voltage and applies an internal reset in the microcontroller when the battery is replaced, etc. If the application circuit satisfies the following conditions, the POC circuit can be incorporated by the mask option. * High reliability is not required. * Clock frequency fX = 2.4 to 8 MHz * Operating ambient temperature TA = -40 to +85C Cautions 1. The one-time PROM product (PD6P4B) already contains the POC circuit. 2. There are cases in which the POC circuit cannot detect a low power supply voltage of less than 1 ms. Therefore, if the power supply voltage has become low for a period of less than 1 ms, the POC circuit may malfunction because it does not generate an internal reset signal. 3. Clock oscillation is stopped by the resonator due to low power supply voltage before the POC circuit generates the internal reset signal. In this case, malfunction may result, for example when the power supply voltage is recovered after the oscillation is stopped. This type of phenomenon takes place because the POC circuit does not generate an internal reset signal (because the power supply voltage recovers before the low power supply voltage is detected) even though the clock has stopped. If, by any chance, a malfunction has taken place, remove the battery for a short time and put it back. In most cases, normal operation will be resumed. 4. If the application circuit does not satisfy the conditions above, design the application circuit so that the reset takes effect without failure within the power supply voltage range by means of an external reset circuit. 5. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is released (when the RESET pin changes from low level to high level, or POC is released due to supply voltage startup). Remarks 1. It is recommended that the POC circuit be incorporated when the application circuit is an infrared remote-control transmitter for household appliances. 2. Even when a POC circuit is incorporated, the externally input RESET is valid with the OR condition; therefore, the POC circuit and the RESET input can be used at the same time. However, if the POC circuit detects a low power supply voltage, the RESET pin will be forced to low level; therefore, use an N-ch open drain output or NPN open collector output for the external reset circuit.
Data Sheet U14474EJ1V0DS00
27
PD62A
7.1 Functions of POC Circuit
The POC circuit has the following functions: * Generating an internal reset signal when VDD VPOC. * Canceling an internal reset signal when VDD > VPOC. Here, VDD: power supply voltage, VPOC: POC-detected voltage.
VDD 3.6 V Clock frequency fX = 2.4 to 8 MHz 2.0 V VPOC 1.7 V (approx.) POC-detected voltage VPOC = 1.85 V (TYP.)Note 3 Operating ambient temperature TA = -40 to +85C
0V
t
Internal reset signal Note 1 Operating mode Reset Note 2
Reset
Notes 1. In reality, oscillation stabilization wait time must elapse before the circuit is switched to operating mode. The oscillation stabilization wait time is about 252/fX to 700/fX (about 70 to 190 s: when fX = 3.64 MHz). 2. For the POC circuit to generate an internal reset signal when the power supply voltage has fallen, it is necessary for the power supply voltage to be kept less than the VPOC for a period of 1 ms or more. Therefore, in reality, there is a time lag of up to 1 ms until the reset takes effect. 3. The POC-detected voltage (VPOC) varies between about 1.7 to 2.0 V; thus, the reset may be canceled at a power supply voltage smaller than the assured range (VDD = 2.0 to 3.6 V). However, as long as the conditions for operating the POC circuit are met, the actual lowest operating power supply voltage becomes lower than the POC-detected voltage. Therefore, there is no malfunction occurring due to the shortage of power supply voltage. However, malfunction for such reasons as the clock not oscillating due to low power supply voltage may occur (refer to Cautions 3. in 7. POC CIRCUIT).
7.2 Oscillation Check at Low Supply Voltage
A reliable reset operation can be expected of the POC circuit if it satisfies the condition that the clock can oscillate even at low power supply voltage (the oscillation start voltage of the resonator being even lower than the POCdetected voltage). Whether this condition is met or not can be checked by measuring the oscillation status on a product which actually contains a POC circuit, as follows. <1> Connect a storage oscilloscope to the XOUT pin so that the oscillation status can be measured. <2> Connect a power supply whose output voltage can be varied and then gradually raise the power supply voltage VDD from 0 V (making sure to avoid VDD > 3.6 V). At first (during VDD < 1.7 V (approx.)), the XOUT pin is 0 V regardless of the VDD. However, at the point that VDD reaches the POC-detected voltage (VPOC = 1.85 V (TYP.)), the voltage of the XOUT pin jumps to about 0.5 VDD. Maintain this power supply voltage for a while to measure the waveform of the XOUT pin. If, by any chance, the oscillation start voltage of the resonator is lower than the POC-detected voltage, the growing oscillation of the XOUT pin can be confirmed within several ms after the VDD has reached the VPOC.
28
Data Sheet U14474EJ1V0DS00
PD62A
8. SYSTEM CLOCK OSCILLATOR
The system clock oscillator configuration consists of a ceramic resonator oscillation circuit (fX = 2.4 to 8 MHz). Figure 8-1. System Clock
PD62A
XOUT
XIN
GND
Ceramic resonator
The system clock oscillator stops its oscillation when reset or in STOP mode. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wire near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as the ground. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator.
Data Sheet U14474EJ1V0DS00
29
PD62A
9. INSTRUCTION SET 9.1 Machine Language Output by Assembler
The bit length of the machine language of this product is 10 bits per word. However, the machine language that is output by the assembler is extended to 16 bits per word. As shown in the example below, the extension is made by inserting 3-bit extended bits (111) in two locations. Figure 9-1. Example of Assembler Output (10 Bits Extended to 16 Bits) <1> In the case of "ANL A, @R0H"
1
1010
1
0000
111
1
1010
111
1
0000
= FAF0
Extended bits
Extended bits
<2> In the case of "OUT P0, #data8"
0
0110
1
1000
111
0
0110
111
1
1000
= E6F8
Extended bits
Extended bits
30
Data Sheet U14474EJ1V0DS00
PD62A
9.2 Circuit Symbol Description
A: ASR: addr: CY: data4: data8: data10: F: PC: Pn: P0n: P1n: ROMn: Rn: R0n: R1n: SP: T: T0: T1: (x): Accumulator Address Stack Register Program memory address Carry flag 4-bit immediate data 8-bit immediate data 10-bit immediate data Status flag Program Counter Port register pair (n = 0, 1, 3, 4) Port register (low-order 4 bits) Port register (high-order 4 bits) Bit n of the program memory's (n = 0 to 9) Register pair Data memory (General-purpose register; n = 0 to F) Data memory (General-purpose register; n = 0 to F) Stack Pointer Timer register Timer register (low-order 4 bits) Timer register (high-order 4 bits) Content addressed with x
Data Sheet U14474EJ1V0DS00
31
PD62A
9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table
Accumulator Operation Instructions
Instruction Code 1st Word ANL A, R0n A, R1n A, @R0H FBEn FAEn FAF0 2nd Word 3rd Word CY A3 * Rmn3 CY A3 * ROM7 A, @R0L FBF0 CY A3 * ROM3 A, #data4 FBF1 data4 CY A3 * data43 ORL A, R0n A, R1n A, @R0H FDEn FCEn FCF0 (A) (A) (Rmn) m = 0, 1 n = 0 to F CY 0 (A) (A) ((P13), (R0))7-4 CY 0 A, @R0L FDF0 (A) (A) ((P13), (R0))3-0 CY 0 A, #data4 FDF1 data4 (A) (A) data4 CY 0 XRL A, R0n A, R1n A, @R0H F5En F4En F4F0 (A) (A) (Rmn) m = 0, 1 n = 0 to F CY A3 * Rmn3 (A) (A) ((P13), (R0))7-4 CY A3 * ROM7 A, @R0L F5F0 (A) (A) ((P13), (R0))3-0 CY A3 * ROM3 A, #data4 F5F1 data4 (A) (A) data4 CY A3 * data43 INC A F4F3 (A) (A) + 1 if (A) = 0 CY 1 else CY 1 RL A FCF3 (An+1) (An), (A0) (A3) CY A3 RLZ A FEF3 if A = 0 CY A3 reset else (An+1) (An), (A0) (A3) 1 2 1 2 1

Mnemonic
Operand
Operation (A) (A) (Rmn) m = 0, 1 n = 0 to F
Instruction Length 1
Instruction Cycle 1
(A) (A) (A) (A)
32
Data Sheet U14474EJ1V0DS00
(A) (A)
((P13), (R0))7-4
((P13), (R0))3-0
data4
2
PD62A
Input/output Instructions
Instruction Code 1st Word IN A, P0n A, P1n OUT P0n, A P1n, A ANL A, P0n A, P1n ORL A, P0n A, P1n XRL A, P0n A, P1n FFF8 + n FEF8 + n E5F8 + n E4F8 + n FBF8 + n FAF8 + n FDF8 + n FCF8 + n F5F8 + n F4F8 + n 2nd Word -- -- -- -- -- -- -- -- -- -- 3rd Word -- -- -- -- -- -- -- -- -- -- CY A3 * Pmn3 (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY 0 (A) (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4 CY A3 * Pmn3 Instruction Length (Pn) data8 n = 0, 1, 3, 4 2 1 Instruction Cycle (A) (Pmn) CY 0 (Pmn) (A) m = 0, 1 n = 0, 1, 3, 4 m = 0, 1 n = 0, 1, 3, 4 1 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
Mnemonic OUT
Operand
Instruction Code 1st Word 2nd Word data8 3rd Word
Pn, #data8 E6F8 + n
Remark
Pn: P1n to P0n are dealt with in pairs.
Data Transfer Instruction
Instruction Code 1st Word MOV A, R0n A, R1n A, @R0H FFEn FEEn FEF0 2nd Word 3rd Word (A) (Rmn) CY 0 (A) ((P13), (R0))7-4 CY 0 A, @R0L FFF0 (A) ((P13), (R0))3-0 CY 0 A, #data4 R0n, A R1n, A FFF1 E5En E4En data4 (A) data4 CY 0 (Rmn) (A) m = 0, 1 n = 0 to F 2 1 m = 0, 1 n = 0 to F 1 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Mnemonic MOV
Operand Rn, #data8 E6En Rn, @R0 E7En
Instruction Code 1st Word 2nd Word data8 -- 3rd Word -- --
(R1n-R0n) data8
(R1n-R0n) ((P13), (R0)) n = 1 to F
Remark
Rn: R1n to R0n are dealt with in pairs.
Data Sheet U14474EJ1V0DS00
(A) (A)
(Pmn) m = 0, 1 n = 0, 1, 3, 4
Operation
Operation
Operation n = 0 to F
Instruction Length 2 1
Instruction Cycle 1
33
PD62A
Branch Instructions
Instruction Code 1st Word JMP addr (Page 0) E8F1 addr (Page 1) E9F1 JC addr (Page 0) ECF1 addr (Page 1) EAF1 JNC addr (Page 0) EDF1 addr (Page 1) EBF1 JF addr (Page 0) EEF1 addr (Page 1) F0F1 JNF addr (Page 0) EFF1 addr (Page 1) F1F1 2nd Word addr addr addr addr addr addr addr addr addr addr if CY = 1 PC addr PC addr PC addr PC addr else PC PC + 2 if CY = 0 else PC PC + 2 if F = 1 else PC PC + 2 if F = 0 else PC PC + 2 3rd Word PC addr 2 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics. Subroutine Instructions
Instruction Code 1st Word CALL addr (Page 0) E6F2 addr (Page 1) E6F2 RET E8F2 2nd Word E8F1 E9F1 3rd Word addr addr PC ASR, SP SP - 1 1 1 SP SP + 1, ASR PC, PC addr 3 Instruction Length 2 Instruction Cycle
Mnemonic
Operand
Operation
Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics. Timer Operation Instructions
Instruction Code 1st Word MOV A, T0 A, T1 T0, A T1, A FFFF FEFF E5FF F4FF 2nd Word 3rd Word (A) (Tn) CY 0 (Tn) (A) (T) n 0 Instruction Code 1st Word MOV T, #data10 T, @R0 E6FF F4FF 2nd Word data10 3rd Word (T) data10 (T) ((P13), (R0)) 1 Instruction Length 1 Instruction Cycle n = 0, 1 n = 0, 1 1 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
Mnemonic
Operand
Operation
34
Data Sheet U14474EJ1V0DS00
PD62A
Others
Instruction Code 1st Word HALT STTS #data4 #data4 E2F1 E3F1 2nd Word data4 data4 3rd Word Standby mode If statuses match else R0n E3En F0 F1 n = 0 to F CY 1 1 F0 CY 0 F1 2 Instruction Length 1 Instruction Cycle
Mnemonic
Operand
Operation
If statuses match else
SCAF
FAF3
If A = 0FH else
NOP
E0E0
PC PC + 1
Data Sheet U14474EJ1V0DS00
35
PD62A
9.4 Accumulator Operation Instructions
ANL A, R0n ANL A, R1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 0 1 R4 0 R3 R2 R1 R0
1 CY A3 * Rmn3

(A) (A)
(Rmn)
m = 0, 1
n = 0 to F
The accumulator contents and the register Rmn contents are ANDed and the results are entered in the accumulator. ANL A, @R0H ANL A, @R0L <1> Instruction code: <2> Cycle count: <3> Function:
1 1 0 1 0/1 1 0 0 0 0
1 (A) (A) (A) (A) ((P13), (R0))7-4 (in the case of ANL A, @R0H) ((P13), (R0))3-0 (in the case of ANL A, @R0L) CY A3 * ROM7 CY A3 * ROM3
The accumulator contents and the program memory contents specified with the control register P13 and register pair R10-R00 are ANDed and the results are entered in the accumulator. If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect. * Program memory (ROM) organization
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
H
L
Valid bits at the time of accumulator operation
ANL A, #data4 <1> Instruction code: <2> Cycle count: <3> Function:
1 101110001 0 0 0 0 0 0 d3 d2 d1 d0
1 (A) (A) data4 CY A3 * data43
The accumulator contents and the immediate data are ANDed and the results are entered in the accumulator.
36
Data Sheet U14474EJ1V0DS00
PD62A
ORL A, R0n ORL A, R1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 0 R4 0 R3 R2 R1 R0
1 (A) (A) (Rmn) CY 0 m = 0, 1 n = 0 to F
The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator. ORL A, @R0H ORL A, @R0L <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 0 0/1 1 0 0 0 0
1 (A) (A) (P13), (R0))7-4 (in the case of ORL A, @R0H) (A) (A) (P13), (R0))3-0 (in the case of ORL A, @R0L) CY 0
The accumulator contents and the program memory contents specified with the control register P13 and register pair R10-R00 are ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect. ORL A, #data4 <1> Instruction code: <2> Cycle count: <3> Function:
1 110110001 0 0 0 0 0 0 d3 d2 d1 d0
1 (A) (A) data4 CY 0
The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. XRL A, R0n XRL A, R1n <1> Instruction code: <2> Cycle count: <3> Function:
1 0 1 0 R4 0 R3 R2 R1 R0
1 (A) (A) (Rmn) CY A3 * Rmn3 m = 0, 1 n = 0 to F
The accumulator contents and the register Rmn contents are ORed and the results are entered in the accumulator.
Data Sheet U14474EJ1V0DS00
37
PD62A
XRL A, @R0H XRL A, @R0L <1> Instruction code: <2> Cycle count: <3> Function:
1 0 1 0 0/1 1 0 0 0 0
1 (A) (A) ((P13), (R0))7-4 (in the case of XRL A, @R0H) CY A3 * ROM7 (A) (A) ((P13), (R0))3-0 (in the case of XRL A, @R0L) CY A3 * ROM3
The accumulator contents and the program memory contents specified with the control register P13 and register pair R10-R00 are exclusive-ORed and the results are entered in the accumulator. If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect. XRL A, #data4 <1> Instruction code: <2> Cycle count: <3> Function:
1 010110001 0 0 0 0 0 0 d3 d2 d1 d0
1 (A) (A) data4 CY A3 * data43
The accumulator contents and the immediate data are exclusive-ORed and the results are entered in the accumulator. INC A <1> Instruction code: <2> Cycle count: <3> Function:
1 010010011
1 (A) (A) + 1 If A=0 CY 1 else CY 0
The accumulator contents are incremented (+1). RL A <1> Instruction code: <2> Cycle count: <3> Function:
1 110010011
1 (An + 1) (An), (A0) (A3) CY A3
The accumulator contents are rotated anticlockwise bit by bit. RLZ A <1> Instruction code: <2> Cycle count: <3> Function:
1 111010011
1 If A=0 reset else (An + 1) (An), (A0) (A3)
CY A3 The accumulator contents are rotated anticlockwise bit by bit. If A = 0H at the time of command execution, an internal reset takes effect.
38
Data Sheet U14474EJ1V0DS00
PD62A
9.5 Input/Output Instructions
IN A, P0n IN A, P1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 1 P4 1 1 P2 P1 P0
1 (A) (Pmn) CY 0 m = 0, 1 n = 0, 1, 3, 4
The port Pmn data is loaded (read) onto the accumulator. OUT P0n, A OUT P1n, A <1> Instruction code: <2> Cycle count: <3> Function:
0 0 1 0 P4 1 1 P2 P1 P0
1 (Pmn) (A) m = 0, 1 n = 0, 1, 3, 4
The accumulator contents are transferred to port Pmn to be latched. ANL A, P0n ANL A, P1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 0 1 P4 1 1 P2 P1 P0
1 CY A3 * Pmn
(A) (A)
(Pmn)
m = 0, 1
n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are ANDed and the results are entered in the accumulator. ORL A, P0n ORL A, P1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 0 P4 1 1 P2 P1 P0
1 (A) (A) (Pmn) CY 0 m = 0, 1 n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are ORed and the results are entered in the accumulator. XRL A, P0n XRL A, P1n <1> Instruction code: <2> Cycle count: <3> Function:
1 0 1 0 P4 1 1 P2 P1 P0
1 (A) (A) (Pmn) CY A3 * Pmn m = 0, 1 n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered in the accumulator.
Data Sheet U14474EJ1V0DS00
39
PD62A
OUT Pn, #data8 <1> Instruction code: : <2> Cycle count: <3> Function:
0 0 1 1 0 1 1 P2 P1 P0 0 d7 d6 d5 d4 0 d3 d2 d1 d0
1 (Pn) data8 n = 0, 1, 3, 4
The immediate data is transferred to port Pn. In this case, port Pn refers to P1n-P0n operating in pairs.
9.6 Data Transfer Instruction
MOV A, R0n MOV A, R1n <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 1 R4 0 R3 R2 R1 R0
1 (A) (Rmn) CY 0 m = 0, 1 n = 0 to F
The register Rmn contents are transferred to the accumulator. MOV A, @R0H <1> Instruction code: <2> Cycle count: <3> Function:
1 111010000
1 (A) ((P13), (R0))7-4 CY 0
The high-order 4 bits (b7 b6 b5 b4) of the program memory specified with control register P13 and register pair R10-R00 are transferred to the accumulator. b9 is ignored. MOV A, @R0L <1> Instruction code: <2> Cycle count: <3> Function:
1 111110000
1 (A) ((P13), (R0))3-0 CY 0
The low-order 4 bits (b3 b2 b1 b0) of the program memory specified with control register P13 and register pair R10-R00 are transferred to the accumulator. b8 is ignored. * Program memory (ROM) contents
@R0 H b9 b7 b6 b5 b4 b8 b3
@R0 L b2 b1 b0
MOV A, #data4 <1> Instruction code: : <2> Cycle count: <3> Function:
1 111110001 0 0 0 0 0 0 d3 d2 d1 d0
1 (A) data4 CY 0
The immediate data is transferred to the accumulator.
40
Data Sheet U14474EJ1V0DS00
PD62A
MOV R0n, A MOV R1n, A <1> Instruction code: <2> Cycle count: <3> Function:
0 0 1 0 R4 0 R3 R2 R1 R0
1 (Rmn) (A) m = 0, 1 n = 0 to F
The accumulator contents are transferred to register Rmn. MOV Rn, #data8 <1> Instruction code: : <2> Cycle count: <3> Function: pairs. The pair combinations are as follows: R0 : R10 - R00 R1 : R11 - R01 : RE : R1E - R0E RF : R1F - R0F Lower column Higher column MOV Rn, @R0 <1> Instruction code: <2> Cycle count: <3> Function:
0 0 1 1 1 0 R3 R2 R1 R0 0 0 1 1 0 0 R3 R2 R1 R0 0 d7 d6 d5 d4 0 d3 d2 d1 d0
1 (R1n-R0n) data8 n = 0 to F
The immediate data is transferred to the register. Using this instruction, registers operate as register
1 (R1n-R0n) ((P13), R0)) n = 1 to F
The program memory contents specified with control register P13 and register pair R10-R00 are transferred to register pair R1n-R0n. The program memory consists of 10 bits and has the following state after the transfer to the register.
Program memory b9 b7 b6 b5 b4 @R0 b8 b3 b2 b1 b0
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
R1n
R0n
The high-order 2 bits of the program memory address is specified with the control register (P13).
Data Sheet U14474EJ1V0DS00
41
PD62A
9.7 Branch Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as follows.
PD62A (ROM: 0.5 K steps): PD6P4B (PROM: 1 K steps) :
JMP addr <1> Instruction code: page 0 <2> Cycle count: <3> Function: a0). JC addr <1> Instruction code: page 0 <2> Cycle count: <3> Function: 1 If CY = 1 1 PC addr
page 0 page 0
0100010001
; page 1
0100110001
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
The 10 bits (PC9-0) of the program counter are replaced directly by the specified address addr (a9 to
0110010001
; page 1
0101010001
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
PC addr
else
PC PC + 2
If the carry flag CY is set (to 1), a jump is made to the address specified with addr (a9 to a0). JNC addr <1> Instruction code: page 0 <2> Cycle count: <3> Function: 1 If CY = 0 else PC addr PC PC + 2
0110110001
; page 1
0101110001
a9 a7 a6 a5 a4 a8 a3 a2 a1a0
If the carry flag CY is cleared (to 0), a jump is made to the address specified with addr (a9 to a0). JF addr <1> Instruction code: page 0 <2> Cycle count: <3> Function: 1 If F=1 else PC addr PC PC + 2
0111010001
; page 1
1000010001
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
If the status flag F is set (to 1), a jump is made to the address specified with addr (a9 to a0). JNF addr <1> Instruction code: page 0 <2> Cycle count: <3> Function: 1 If F=0 PC addr else PC PC + 2
0111110001
; page 1
1000110001
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
If the status flag F is cleared (to 0), a jump is made to the address specified with addr (a9 to a0).
42
Data Sheet U14474EJ1V0DS00
PD62A
9.8 Subroutine Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as follows.
PD62A (ROM: 0.5 K steps):
page 0
PD6P4B (PROM: 1 K steps): page 0
CALL addr <1> Instruction code:
0 011010010
page 0 <2> Cycle count: <3> Function: 2
0100010001
; page 1
0100110001
a9 a7 a6 a5 a4 a8 a3 a2 a1 a0
SP SP + 1 ASR PC PC addr
The stack pointer value is incremented (+1) and the program counter value is saved in the address stack register. Then, the address specified with the operand addr (a9 to a0) is entered in the program counter. If a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect. RET <1> Instruction code: <2> Cycle count: <3> Function:
0 100010010
1 PC ASR SP SP - 1
The value saved in the address stack register is restored to the program counter. Then, the stack pointer is decremented (-1) . If a borrow is generated when the stack pointer value is decremented (-1), an internal reset takes effect.
Data Sheet U14474EJ1V0DS00
43
PD62A
9.9 Timer Operation Instructions
MOV A, T0 MOV A, T1 <1> Instruction code: <2> Cycle count: <3> Function:
1 1 1 1 0/1 1 1 1 1 1
1 (A) (Tn) CY 0 n = 0, 1
The timer Tn contents are transferred to the accumulator. T1 corresponds to (t9, t8, t7, t6); T0 corresponds to (t5, t4, t3, t2).
T t9 t8 T1 t7 t6 t5 t4 T0 t3 t2 t1 t0
MOV T, #data10 Can be set with MOV T, @R0
MOV T0, A MOV T1, A <1> Instruction code: <2> Cycle count: <3> Function:
0 0 1 0 0/1 1 1 1 1 1
1 (Tn) (A) n = 0, 1
The accumulator contents are transferred to the timer register Tn. T1 corresponds to (t9, t8, t7, t6); T0 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to T1, t1 becomes 0; if data is transferred to T0, t0 becomes 0. MOV T, #data10 <1> Instruction code: <2> Cycle count: <3> Function:
0 011011111 t1 t9 t8 t7 t6 t0 t5 t4 t3 t2
1 (T) data10
The immediate data is transferred to the timer register T (t9-t0). Remark The timer time is set with (set value + 1) x 64/fX or 128/fX.
44
Data Sheet U14474EJ1V0DS00
PD62A
MOV T, @R0 <1> Instruction code: <2> Cycle count: <3> Function:
0 011111111
1 (T) ((P13), (R0))
The program memory contents are transferred to the timer register T (t9 to t0) specified with the control register P13 and the register pair R10-R00. The program memory, which consists of 10 bits, is placed in the following state after being transferred to the register.
Program memory t1 t9 t8 t7 t6 @R0 t0 t5 t4 t3 t2
Timer T
t9
t8 T1
t7
t6
t5
t4 T0
t3
t2
t1
t0
The high-order 2 bits of the program memory address are specified with the control register (P13). Caution When setting a timer value in the program memory, be sure to use the DT directive.
9.10 Others
HALT #data4 <1> Instruction code: : <2> Cycle count: <3> Function:
0 001010001 0 0 0 0 0 0 d3 d2 d1 d0
1 Standby mode
Places the CPU in standby mode. The condition for having the standby mode (HALT/STOP mode) canceled is specified with the immediate data. STTS R0n <1> Instruction code: <2> Cycle count: <3> Function:
0 0 0 1 1 0 R3 R2 R1 R0
1 If statuses match else F0 F1 n = 0 to F
The S0, S1, KI/O, KI, and TIMER statuses are compared with the register R0n contents. If at least one of the statuses coincides with the bits that have been set, the status flag F is set (to 1). If none of them coincide, the status flag F is cleared (to 0).
Data Sheet U14474EJ1V0DS00
45
PD62A
STTS #data4 <1> Instruction code: : <2> Cycle count: <3> Function:
0 001110001 0 0 0 0 0 0 d3 d2 d1 d0
1 if statuses match else F0 F1
The S0, S1, KI/O, KI, and TIMER statuses are compared with the immediate data contents. If at least one of the statuses coincides with the bits that have been set, the status flag F is set (to 1). If none of them coincide, the status flag F is cleared (to 0). SCAF (Set Carry If ACC = FH) <1> Instruction code: <2> Cycle count: <3> Function:
1 101010011
1 if A = 0FH CY 1 else CY 0
The carry flag CY is set (to 1) if the accumulator contents are FH. The accumulator values after executing the SCAF instruction are as follows:
Accumulator Value Before execution xxx0 xx01 x011 0111 1111 After execution 0000 0001 0011 0111 1111 0 (clear) 0 (clear) 0 (clear) 0 (clear) 1 (set)
Carry Flag
Remark NOP
x: don't care
<1> Instruction code: <2> Cycle count: <3> Function: No operation
0 000000000
1 PC PC + 1
46
Data Sheet U14474EJ1V0DS00
PD62A
10. ASSEMBLER RESERVED WORDS 10.1 Mask Option Directives
When creating the PD62A program, it is necessary to use a mask option directive in the assembler's source program to specify a mask option. 10.1.1 OPTION and ENDOP directives The assembler directives from the OPTION directive to the ENDOP directive are called the mask option definition block. The format of the mask option definition block is as follows: Format Symbol field [Label:] Mnemonic field OPTION : : ENDOP 10.1.2 Mask option definition directive The assembler directives that can be used in the mask option definition block are listed in Table 10-1. An example of the mask option definition is shown below. Example Symbol field Mnemonic field OPTION USEPOC ENDOP Table 10-1. List of Mask Option Definition Directives
PRO File Address Value POC USEPOC (With POC circuit) NOUSEPOC (Without POC circuit) 2044H Data Value 01 00
Operand field
Comment field [; Comment]
Operand field
Comment field ; POC circuit incorporated
Name
Mask Option Definition Directive
Data Sheet U14474EJ1V0DS00
47
PD62A
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25C)
Parameter Power supply voltage Input voltage Output voltage Output current, high Symbol VDD VI VO IOHNote REM Peak value rms LED Peak value rms One KI/O pin Peak value rms Total of LED and KI/O pins IOL Note Peak value rms Output current, low REM Peak value rms LED Peak value rms Operating ambient temperature Storage temperature TA Tstg KI/O, KI, S0, S1, RESET Conditions Rating -0.3 to +3.8 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -30 -20 -7.5 -5 -13.5 -9 -18 -12 7.5 5 7.5 5 -40 to +85 -65 to +150 Unit V V V mA mA mA mA mA mA mA mA mA mA mA mA C C
Note The rms value should be calculated as follows: [rms value] = [Peak value] x
Duty.
Caution Product quality may suffer if the absolute rating is exceeded even momentarily for any parameter. That is, the absolute maxumum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure the absolute maximum ratings are not exceeded. Recommended Power Supply Voltage Range (TA = -40 to +85C)
Parameter Power supply voltage Symbol VDD Conditions fX = 2.4 to 8 MHz MIN. 2.0 TYP. 3.0 MAX. 3.6 Unit V
48
Data Sheet U14474EJ1V0DS00
PD62A
DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V)
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 Input voltage, low VIL1 VIL2 VIL3 Input leakage current, high ILIH2 Input leakage current, low ILIL1 ILIL2 ILIL3 Output voltage, high Output voltage, low VOH1 VOL1 VOL2 Output current, high IOH1 IOH2 Output current, low IOL1 ILIH1 RESET KI/O KI, S0, S1 RESET KI/O KI, S0, S1 KI VI = VDD, pull-down resistor not incorporated S0, S1 VI = VDD, pull-down resistor not incorporated KI KI/O S0, S1 VI = 0 V VI = 0 V VI = 0 V IOH = -0.3 mA IOL = 0.3 mA IOL = 15 A VDD = 3.0 V, VOH = 1.0 V VDD = 3.0 V, VOH = 2.2 V VDD = 3.0 V, VOL = 0.4 V VDD = 3.0 V, VOL = 2.2 V On-chip pull-up resistor On-chip pull-down resistor R1 R2 R3 R4 Data retention power supply voltage Supply currentNote VDDDR IDD1 RESET RESET KI, S0, S1 KI/O In STOP mode Operating mode IDD2 HALT mode fX = 8.0 MHz, VDD = 3 V 10% fX = 4.0 MHz, VDD = 3 V 10% fX = 8.0 MHz, VDD = 3 V 10% fX = 4.0 MHz, VDD = 3 V 10% IDD3 STOP mode VDD = 3 V 10%, When POC circuit incorporated by mask option VDD = 3 V 10%, TA = 25C, When POC circuit incorporated by mask option -5 -2.5 30 100 25 2.5 75 130 0.9 0.8 0.7 0.75 0.65 1.9 1.9 -12 -7 70 390 50 5 150 250 100 15 300 500 3.6 1.6 1.4 1.5 1.3 9.0 5.0 0.8 VDD 0.3 0.4 Conditions MIN. 0.8 VDD 0.7 VDD 0.65 VDD 0 0 0 TYP. MAX. VDD VDD VDD 0.2 VDD 0.3 VDD 0.15 VDD 3 3 -3 -3 -3 Unit V V V V V V
A A A A A
V V V mA mA
REM, LED, KI/O REM, LED KI/O REM KI/O KI/O
A A
k k k k V mA mA mA mA
A A
Note The current flowing to the on-chip pull-up resistors is not included.
Data Sheet U14474EJ1V0DS00
49
PD62A
AC Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V)
Parameter Symbol Test Conditions MIN. 7.9 10 When releasing standby mode RESET low-level width tRSL In HALT mode In STOP mode 10 Note 10 TYP. MAX. 27 Unit
Instruction execution time tCY KI, S0, S1 high-level width tH
s s s s s
Note 10 + 52/fX + oscillation growth time Remark tCY = 64/fX (fX: System clock oscillation frequency) POC Circuit (mask optionNote 1) (TA = -40 to +85C)
Parameter POC-detected voltageNote 2 Symbol VPOC Test Conditions MIN. TYP. 1.85 MAX. 2.0 Unit V
Notes 1. Operates effectively under the conditions of fX = 2.4 to 8 MHz. 2. Refers to the voltage at which the POC circuit cancels an internal reset. If VPOC < VDD, the internal reset is released. From the time of VPOC VDD until the internal reset takes effect, a delay of up to 1 ms occurs. When the period of VPOC VDD lasts less than 1 ms, the internal reset may not take effect. System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0 to 3.6 V)
Parameter Oscillation frequency (ceramic resonator) Symbol fX Conditions MIN. 2.4 TYP. 3.64 MAX. 8.0 Unit MHz
50
Data Sheet U14474EJ1V0DS00
PD62A
Recommended Ceramic Resonator (TA = -40 to +85C)
Frequency Recommended Constant (MHz) C1 [pF] C2 [pF] 3.52 3.58 3.64 3.84 4.0 6.0 8.0 2.5 100 100 Unnecessary (C-containing type) Power Supply Voltage [V] MIN. 2.0 MAX. 3.6
Manufacturer
Part Number
Remark
TDK Corp.
FCR3.52MC5 FCR3.58MC5 FCR3.64MC5 FCR3.84MC5 FCR4.0MC5 FCR6.0MC5 FCR8.0MC5
Murata Mfg. Co., Ltd
CSA2.50MG040 CST2.50MG040
Unnecessary (C-containing type) 3.52 30 30
CSA3.52MG CST3.52MGW CSTS0352MG03 CSA3.58MG CST3.58MGW CST0358MG03 CSA3.64MG CST3.64MGW CSTS0364MG03 CSA3.84MG CST3.84MGW CST0384MG03 CSA4.00MG CST4.00MGW CSTS0400MG03 CSA6.00MG CST6.00MGW CSTS0600MG03 CSA8.00MTZ CST8.00MTW CSTS0800MG03
Unnecessary (C-containing type) 3.58 30 30
Unnecessary (C-containing type) 3.64 30 30
Unnecessary (C-containing type) 3.84 30 30
Unnecessary (C-containing type) 4.0 30 30
Unnecessary (C-containing type) 6.0 30 30
Unnecessary (C-containing type) 8.0 30 30
Unnecessary (C-containing type)
An external circuit example
XIN
XOUT
C1
C2
Data Sheet U14474EJ1V0DS00
51
PD62A
12. CHARACTERISTICS CURVES (REFERENCE VALUES)
IDD vs VDD (fx = 4 MHz) (TA = 25C) 1 0.9 Power supply current IDD [mA] Power supply current IDD [mA] 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.6 4 HALT mode Operating mode 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.6 4 HALT mode Operating mode IDD vs VDD (fx = 8 MHz) (TA = 25C)
Power supply voltage VDD [V]
Power supply voltage VDD [V]
IOL vs VOL (REM, LED) (TA = 25C, VDD = 3.0 V) 25 High-level output current IOH [mA]
- 20 - 18 - 16 - 14 - 12 - 10 -8 -6 -4 -2 0 VDD
IOH vs VOH (REM, LED, KI/O) (TA = 25C, VDD = 3.0 V)
Low-level output current IOL [mA]
20
15
10
5
0
1
2
3
VDD - 1
VDD - 2
VDD - 3
Low-level output voltage VOL [V]
High-level output voltage VOH [V]
IOL vs VOL (KI/O) (TA = 25C, VDD = 3.0 V) 500 450 Low-level output current IOL [ A] 400 350 300 250 200 150 100 50 0 1 2 Low-level output voltage VOL [V] 3
Data Sheet U14474EJ1V0DS00
52
PD62A
13. APPLICATION CIRCUIT EXAMPLE
Example of Application to System * Remote-control transmitter (40 keys; mode selection switch accommodated)
KI/O6 KI/O7 S0 + S1/LED REM VDD + XOUT XIN GND RESET
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0 Key matrix 8 x 5 = 40 keys Mode selection switch
* Remote-control transmitter (48 keys accommodated)
KI/O6 KI/O7 S0 + S1/LED REM VDD + XOUT XIN GND RESET
KI/O5 KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0 Key matrix 8 x 6 = 48 keys
Remark When the POC circuit of the mask option is used effectively, it is not necessary to connect the capacitor enclosed in the broken lines.
Data Sheet U14474EJ1V0DS00
53
PD62A
14. PACKAGE DRAWINGS
20 PIN PLASTIC SSOP (300 mil)
20 11
detail of lead end F G T
P E 1 A H I S 10
L U
J
N C D
NOTE
S K
M
M
B
ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 6.650.15 0.475 MAX. 0.65 (T.P.) 0.24 +0.08 -0.07 0.10.05 1.30.1 1.2 8.10.2 6.10.2 1.00.2 0.170.03 0.5 0.13 0.10 3 +5 -3 0.25 0.60.15 S20MC-65-5A4-1
Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition.
Remark The dimensions and materials of the ES model are the same as those of the mass production model.
54
Data Sheet U14474EJ1V0DS00
PD62A
15. RECOMMENDED SOLDERING CONDITIONS
The PD62A should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representatives. Table 15-1. Surface Mounting Type Soldering Conditions
PD62AMC-xxx-5A4: 20-pin plastic SSOP (300 mils)
Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1 --
Soldering Method Infrared reflow VPS Wave soldering Partial heating
Soldering Conditions Package peak temperature: 235C; Time: 30 seconds max. (at 210C or higher); Count: three times or less Package peak temperature: 215C; Time: 40 seconds. max. (at 200C or higher); Count: Three times or less Solder bath temperature: 260C max.; Time: 10 seconds max.; Count: once; Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C or less; Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U14474EJ1V0DS00
55
PD62A
APPENDIX A. DEVELOPMENT TOOLS
An emulator is provided for emulating the PD62A. Hardware * Emulator (EB-6133Note) Used to emulate the PD62A. Note This is a product made by Naito Densei Machida Mfg. Co., Ltd. For details, contact Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813). Software * Assembler (AS6133) * This is a development tool for remote control transmitter software. Part Number List of AS6133
Host Machine PC-9800 series (CPU: 80386 or more) IBM PC/ATTM and compatibles MS-DOS (Ver. 6.0 to Ver. 6.22) PC DOSTM (Ver. 6.1 to Ver. 6.3) 3.5-inch 2HC OS MS-DOSTM (Ver. 5.0 to Ver. 6.2) Supply Medium 3.5-inch 2HD Part Number
S5A13AS6133 S7B13AS6133
Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this software.
56
Data Sheet U14474EJ1V0DS00
PD62A
APPENDIX B. FUNCTIONAL COMPARISON BETWEEN PD62A AND OTHER SUBSERIES
Item ROM capacity RAM capacity Stack Key matrix S0 (S-IN) input S1/LED (S-OUT) Clock frequency
PD62A
512 x 10 bits 32 x 4 bits
PD63A
768 x 10 bits
PD64
PD6134
PD6600A
512 x 10 bits 32 x 5 bits 3 levels (also used for RAM) 8 x 4 = 32 keys Read by left shift instruction Output Ceramic oscillation
1002 x 10 bits 1002 x 10 bits
1 level (also used as RF of RAM) 8 x 6 = 48 keys Read by P01 register (standby release function available) I/O (standby release function available) Ceramic oscillation * fX = 2.4 to 8 MHz * fX = 2.4 to 8 MHz * fX = 2.4 to 4 MHz (with POC circuit)
* fX = 300 kHz to 1 MHz * fX = 400 to 500 kHz * fX = 300 to 500 kHz (with POC circuit) fX/8, fX/16 fX/8 Writing count value and P1 register value * fX, fX/8, fX/12 (timer clock: fX/8) * fX/2, fX/16, fX/24 (timer clock: fX/16) * No carrier * fX/8, fX/12
Timer
Clock Count start
fX/64, fX/128 Writing count value * fX/8, fX/64, fX/96 (timer clock: fX/64) * fX/16, fX/128, fX/192 (timer clock: fX/128) * No carrier
Carrier
Frequency
Output start Instruction execution time Relative branch instruction Left shift instruction Standby mode (HALT instruction) Relationship between HALT instruction execution and status flag (F) Reset function by charging/ discharging capacitor POC circuit
Synchronized with timer 8 s (fX = 8 MHz) None None HALT mode for timer only. STOP mode for only releasing KI (KI/O high-level output or KI/O0 high-level output) HALT instruction not executed when F = 1 8 s (fX = 1 MHz)
Asynchronized with timer 16 s (fX = 500 kHz) Provided Provided n = 0 to F HALT/STOP mode set by P1 register value HALT instruction executed regardless of status of F Provided Provided (low-voltage detection circuit) Low level output to S-OUT pin on detection * Pull-down resistor * Variable duty * Runaway detection VDD = 2.2 to 3.6 V TA = -20 to +70C
"MOV Rn, @RO" instruction n = 1 to F
None Mask option Low level output to RESET pin on detection
Mask option
POC circuit only (set by software in circuits other than POC circuit)
Supply voltage Operating temperature
VDD = 2.0 to 3.6 V VDD = 1.8 to 3.6 V * TA = -40 to +85C * TA = -40 to +85C * TA = -20 to +70C (with POC circuit)
Package
* 20-pin plastic * 20-pin plastic * 20-pin plastic SOP SSOP SOP * 20-pin plastic SSOP
One-time PROM model
PD6P4B
PD61P34B
* 20-pin plastic SOP * 20-pin plastic shrink DIP PD61P24
Data Sheet U14474EJ1V0DS00
57
PD62A
APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT (NEC transmission format in command one-shot transmission mode)
Caution When using the NEC transmission format, apply for a custom code at NEC. (1) REM output waveform (From <2>, the output is made only when the key is continually pressed.)
REM output 58.5 to 76.5 ms <1> 108 ms
<2> 108 ms
Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can be reduced by sending the reader code and the stop bit from the second time. (2) Enlarged waveform of <1>
<3> REM output 9 ms 4.5 ms Custom code 8 bits Custom code' 8 bits Data code 8 bits 27 ms Data code 8 bits Stop bit 1 bit
13.5 ms Leader code
18 to 36 ms 58.5 to 76.5 ms
(3) Enlarged waveform of <3>
REM output 9 ms 13.5 ms 4.5 ms 0.56 ms 1.125 ms 2.25 ms 0 1
1
0
0
(4) Enlarged waveform of <2>
REM output 9 ms 11.25 ms Leader code 2.25 ms 0.56 ms Stop bit
58
Data Sheet U14474EJ1V0DS00
PD62A
(5) Carrier waveform (enlarged waveform of each code's high period)
REM output 8.77 s 26.3 s 9 ms or 0.56 ms Carrier frequency : 38 kHz
(6) Bit array of each code
C0 C1 C2 C3 C4 C5 C6 C7 C0' C1' C2' C3' C4' C5' C6' C7' D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
= = = = = = = =
C0 C1 C2 C3 C4 C5 C6 C7 or or or or or or or or Co C1 C2 C3 C4 C5 C6 C7
Leader code
Custom code
Custom code'
Data code
Data code
Caution To prevent malfunction with other systems when receiving data in the NEC transmission format, not only fully decode (make sure to check Data code as well) the total 32 bits of the 16-bit custom codes (Custom code, Custom code') and the 16-bit data codes (Data code, Data code) but also check to make sure that no signals exist.
Data Sheet U14474EJ1V0DS00
59
PD62A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
60
Data Sheet U14474EJ1V0DS00
PD62A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U14474EJ1V0DS00
61
PD62A
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8

▲Up To Search▲

Price & Availability of UPD62A

	To Download UPD62A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .